The present invention pertains to a novel packet switched router architecture which provides extremely high bandwidth. More particularly, the present invention relates to a bus architecture that performs switching functions in order to allow simultaneous point-to-point communications between multiple devices of a computer system.
In the past, computers were primarily applied to processing rather mundane, repetitive numerical and/or textual tasks involving number-crunching, spread sheeting, and word processing. These simple tasks merely entailed entering data from a keyboard, processing the data according to some computer program, and then displaying the resulting text or numbers on a computer monitor and perhaps later storing these results in a magnetic disk drive. However, today""s computer systems are much more advanced, versatile, and sophisticated. Especially since the advent of digital media applications and the Internet, computers are now commonly called upon to accept and process data from a wide variety of different formats ranging from audio to video and even realistic computer-generated three-dimensional graphic images. A partial list of applications involving these digital media applications include the generation of special effects for movies, computer animation, real-time simulations, video teleconferencing, Internet-related applications, computer games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diagnostic imaging, etc.
The reason behind the proliferation of digital media applications is due to the fact that much more information can be conveyed and readily comprehended with pictures and sounds rather than with text or numbers. Video, audio, and three-dimensional graphics render a computer system more user friendly, dynamic, and realistic. However, the added degree of complexity for the design of new generations of computer systems necessary for processing these digital media applications is tremendous. The ability of handling digitized audio, video, and graphics requires that vast amounts of data be processed at extremely fast speeds. An incredible amount of data must be processed every second in order to produce smooth, fluid, and realistic full-motion displays on a computer screen. Additional speed and processing power is needed in order to provide the computer system with high-fidelity stereo sound and real-time, and interactive capabilities. Otherwise, if the computer system is too slow to handle the requisite amount of data, its rendered images would tend to be small, grainy and otherwise blurry. Furthermore, movement in these images would likely be jerky and disjointed because its update rate is too slow. Sometimes, entire video frames might be dropped. Hence, speed is of the essence in designing modin, state-of-the-art computer systems.
One of the major bottlenecks in designing fast, high-performance computer systems pertains to the current bus architecture. A xe2x80x9cbusxe2x80x9d is comprised of a set of wires that is used to electrically interconnect the various semiconductor chips and input/output devices of the computer system. Electric signals are conducted over the bus so that the various components can communicate with each other. FIG. 1 shows a typical prior art bus architecture. Virtually all of today""s computer systems use this same type of busing scheme. A single bus 101 is used to electrically interconnect the central processing unit (CPU) 103 with the memory (e.g., RAM) 107 via controller 102. Furthermore, other various devices 104-106 are also coupled to bus 101. Bus 101 is comprised of a set of physical wires which are used to convey digital data, address information for specifying the destination of the data, control signals, and timing/clock signals. For instance, CPU 103 may generate a request to retrieve certain data stored in memory 107. This read request is then sent over bus 101 to memory controller 102. Upon receipt of this read request, memory controller 102 fetches the desired data from memory 107 and sends it back over bus 101 to the CPU 103. Once the CPU is finished processing the data, it can be sent via bus 101 for output by one of the devices 104-106 (e.g., fax, modem, network controller, storage device, audio/video driver, etc.).
The major drawback to this prior art bus architecture is the fact that it is a xe2x80x9csharedxe2x80x9d arrangement. All of the components 102-106 share the same bus 101. They all rely on a single bus to meet their individual communication needs. However, bus 101 can only establish communications between two of these devices 102-106 at any given time. Hence, if bus 101 is currently busy transmitting signals between two of the devices (e.g., CPU 103 and device 105), then all the other devices (e.g., memory 107, device 104, and device 106) must wait their turn until that transaction is complete and bus 101 again becomes available. If a conflict arises, an arbitration circuit, usually residing in memory controller 102, resolves which of the devices 104-106 gets priority of access to bus 101. Essentially, bus 101 is analogous to a telephone xe2x80x9cpartyxe2x80x9d line, whereby only one conversation can take place amongst a host of different handsets serviced by the party line. If the party line is currently busy, one must wait until the prior parties hang up, before one can initiate their own call.
In the past, this type of bus architecture offered a simple, efficient, and cost-effective method of transmitting data. For a time, it was also sufficient to handle the trickle of data flowing between the various devices residing within the computer system. However, as the demand for increased amounts of data skyrocketed, designers had to find ways to improve the speed at which bits of data can be conveyed (i.e., increased xe2x80x9cbandwidthxe2x80x9d) over the bus. One temporary solution was to increase the width of the bus by adding more wires. The effect is analogous to replacing a two-lane road with a ten-lane super freeway. However, the increase in bus width consumes valuable space on an already densely packed and overcrowded printed circuit board. Furthermore, each of the semiconductor chips connected to the bus must have an equivalent amount of pins to match the increased bus width for accepting and outputting its signals. These additional pins significantly increase the size of the chips. It becomes more difficult to fit these chips onto the printed circuit boards. Furthermore, the practical limitation for cost effective chips and packages impose a physical restriction on the chip""s overall size and its number of pins. Today""s buses are typically limited to being 64-bits wide. In other words, 64 bits of data or address can be sent simultaneously in parallel over 64 separate wires. The next step of increasing the bus width to 128 bits wide has become impractical.
Another temporary solution to the bandwidth problem was to increase the rate (i.e., frequency) at which data is sent over the bus. However, the physics associated with implementing long sets of parallel wires with multiple loads produces a wide range of problems such as impedance, mismatches, reflections, crosstalk, noise, non-linearities; attenuations, distortions, timing, etc. These problems become even more severe as the frequency increases. It has come to a point where the highest attainable frequency is approximately 33-50 MHz. Higher frequencies cannot be attained without fine tuning, extremely tight tolerances, exotic micro-strip layouts, and extensive testing. It is extremely difficult to reliably mass produce such high frequency computers.
Given a 64-bit bus running at 50 MHz, the highest attainable data rate for a typical computer system is 400 Mbytes per second. Although this data rate appears to be quite impressive, it is nevertheless fast becoming insufficient to meet the demands imposed by tomorrow""s new applications. Thus, there is a great need for some type of bus scheme that provides increased throughput. The present invention offers a unique solution to this problem by providing a novel bus architecture that has a bandwidth which is many times greater than that of typical prior art buses. Furthermore, the bus architecture of the present invention is reliable, cost-effective, and extremely efficient. One fundamental difference is that rather than having a shared bus arrangement, the present invention utilizes a packet switched interconnect scheme whereby multiple packets can be sent concurrently by various devices to different destinations. Hence, the bandwidth associated with the packet switched routing architecture of the present invention is significantly greater because multiple high-speed packet transmissions can occur simultaneously.
The present invention pertains to a novel architecture for establishing multiple, concurrent communications between a plurality of devices. Any number of devices are connected to individual ports of a central packet switched router. Due to the nature of the link between the device and the packet switched routed, very high data rates can be achieved with minimal number of pins. Devices communicate with each other by sending data packets from the originating device to the destination device. Any device can communicate with any other device through the packet switched router. The packet switched router has the capability of simultaneously routing a plurality of packets from a plurality of originating devices to a plurality of destination devices. Hence, multiple high-speed data communications can occur simultaneously, thereby significantly increasing the overall system bandwidth.